(1) Field of the Invention
The invention relates to the field of Semiconductor fabrication, and more specifically to a method of fabricating a self-aligned gate for use in semiconductor devices.
(2) Description of the Prior Art
Semiconductor devices are found in nearly all electronic devices. They can be made in miniature forms for use in integrated circuits. The introduction of the transistor and its continuing development in ever-smaller size is one of the major factors in the continued growth of the application of the transistor in a wide range of electronic devices such as personal computers, calculators and many others.
One type of transistor in wide use is the field effect transistor, which is manufactured and used in a number of varieties such as the metal-semiconductor field effect transistor (MESFET).
A controllable current can be established between the source and the drain electrode of this transistor with the current controlled by a voltage applied to a gate electrode that is positioned on the semiconductor substrate between the source and the gate electrode.
The performance of this type of transistor is, like most types of transistors, determined by its size and the therefrom following performance parameters. For the MESFET specifically the gate electrical resistance and capacitance are of importance. Higher capacitance and resistance are, from a performance point of view, undesirable since this reduces the high frequency performance of this transistor.
As the length of the contact surface or gate of the electrode parallel to the direction of current flow is reduced, the resistance of the gate electrode increases and its capacitance decreases. That is, as the gate length is made shorter, its resistance rises and becomes the dominant factor in limiting the operating frequency of the device.
Accordingly, there exists a need for a gate electrode geometry and fabrication that permits the fabrication of smaller gates for the use in field effect transistors and possibly other electronic devices.
In order to increase the operating frequency of a field effect transistor it is therefore in general required that the length of the gate is reduced. Therefore, in order to prevent increase of the gate resistance while shortening the length of the gate, a method in which a section of the gate has a T form is mostly used.
Current design approaches use the T-shaped gate construct to resolve these problems. The process can be implemented largely with individual processing steps that are known within the state of the art and which are fully compatible with related processing steps of field effect transistors and other semiconductor circuit elements.
It is the primary objective of the present invention to increase the quality of the Titanium Silicon layer, which is deposited on top of the drain and source within the construct of the field effect transistor.
Another objective is to allow fabrication of T-gate field effect transistors with very small gate length. As the gate length is reduced to very small values it becomes increasingly more difficult to form acceptable TiSi.sub.x on top of the gate source and drain areas. The present invention addresses this problem.
U.S. Pat. No. 5,498,560 (Sharma et al.) shows a T shaped gate using an opening and spacer process similar to the invention's 1.sup.st method with the difference that the Sharma does not use a CMP.
U.S. Pat. No. 4,849,376 (Balzan et al.), U.S. Pat. No. 5,688,704 (Liu), U.S. Pat. No. 5,658,826 (Chung), U.S. Pat. No. 5,288,654 (Kasai et al.), U.S. Pat. No. 5,496,779 (Lee et al.), U.S. Pat. No. 4,975,382 (Takasugi), U.S. Pat. No. 4,700,462 (Beaubien) show T shaped gates.
U.S. Pat. No. 5,731,239 (Wong et al.) shows a silicide gate process.